AMD

RTL Design Engineer, PCIe Subsystem

Markham / Vancouver$155K–$233K

Sourced from JD

Every milestone below maps to a skill listed in AMD’s real job posting. No filler chapters, no generic curriculum, just the exact skills the role demands.

0 / 17 topics · 0 / 4 milestones

M1
- SystemVerilog fundamentals Shared · counts toward 4 tracks
  0/10Open
- Micro-architecture: spec → block diagram → RTL
  0/8Open
- VCS simulation & RTL debug
  0/9Open
- Perl / shell scripting
  0/8Open

RTL Design Engineer, PCIe Subsystem

Core RTL Craft

Front-End Signoff Discipline

PCIe Protocol Depth

Tape-Out Ownership & Design Leadership